Snapshot of Capability
Using SimPLL's new PLL Wizard you can design a new PLL
with a few clicks of the mouse. We have just designed one that
tunes from 150MHz to 170MHz in 25kHz steps using a LMX2306 PLL IC and a
MiniCircuits POS300 VCO. SimPLL generates a detailed
schematic of the PLL: 
and
because the LMX2306 and MiniCircuits POS300 are in the libraries,
you haven't had to enter any device data. The PLL has been
designed with a loop bandwidth of 2.5kHz and a phase margin of 45degrees.
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SimPLL predicts the phase noise from the
synthesizer. To evaluate which phase detector current
setting to use we compared the 250uA setting (red trace) to the
1mA setting (blue trace), both with a loop bandwidth of
2.5kHz. The difference is due to the larger loop filter
resistor in the low current case. |
| Showing the effect of 1nA of DC current at the
phase detector. This could be from phase detector
leakage, in some cases from loop filter capacitor leakage or
VCO varactor diode leakage. |
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Modulation frequency response from modulating the
VCO, showing the peaking around the loop bandwidth.
Blue trace is with a 45 degree phase margin, red trace has a
60 degree phase margin to reduce peaking. |
| SimPLL can easily simulate frequency transients -
here from 150Mhz to 170MHz (full band). |
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Loop settling is easily observed on the plot of
|frequency error|. This shows at a glance that the loop
takes about 1.1ms to lock to within 1kHz and 1.5ms to lock within
10Hz |
| The VCO phase error is an important parameter in
many digital communications systems - here we can see that for the
transient plotted above, the VCO takes about 1.1ms to lock
to within 10 degrees of its final phase. |
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SimPLL even provides you with details of the
output of the lock detect filter. Shown here in the
blue trace is the output from the two time constant analog lock
detect filter shown in the schematic, the red trace is the
lock detect output using the LMX2306 digital lock detect
circuit. |
You can vary any of the design parameters (such as loop
bandwidth, phase margin, charge pump current etc) or component
values and watch how the PLL performance changes. Add to
this is a report that you can customize to provide phase noise
details, phase jitter calculations, residual FM, ACI and
ACR calculation. SimPLL even designs and simulates PLL's using
switched loop filters for faster locking. SimPLL will
have you optimising designs in minutes that you had to build and measure
before. |
