|
SimPLL is a complex program for the analysis and
synthesis of PLL frequency synthesizers. A summary of its
features is presented here, we recommend evaluating the
demonstration version for a comprehensive illustration of capability.
PLL
Synthesis: automated design of PLL
synthesizer from requirements, VCO, PLL IC and loop filter
topology. Schematic of PLL IC, loop filter and lock detect
circuit is generated. Frequency
Domain Analysis: open loop gain and phase, phase
noise, reference spurs and modulation response.
Calculation of phase jitter, residual FM and adjacent channel
power. Several phase noise models for VCO and reference.
Optional inclusion of 'divider delay'. Time
Domain Simulation: frequency transient, output
frequency, frequency error, phase error, filtered
lock detect output. Lock times calculated.
Transient simulation includes non-linear effects of charge pump
saturation, phase detector cycle slipping, op-amp clipping (if
active filter) and non-linear VCO tuning law. System
Requirements:
Pentium processor (150MHz or faster
recommended)
Windows 95/98 or later, Windows NT4 or later
32Mb RAM (64Mb or more recommended)
800 x 600 video (1024 x 768 or higher recommended)
|
