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Forums | ADI SimPLL Users' Forum | Error message with ADF7011

Author	Topic
uweren	Posted - 16 October 2003 20:57 I try to make a ADF7011 433 MHz design. I use ADSIMPLL. I receive the following error message and I am not aware on how to change parameters to avoid such messages. The message is: "Error 1001: Time Domain - Loop cannot lock at start frequency. -10.173125 Volts is out of Phase Detector Range Processing Terminated due to error 0 warnings, processing complete" Can anybody help me what are next steps to proceed. Thank you Cheers uwe renschler uwe@renschler.de
Peter White	Posted - 17 October 2003 16:24 uwe, this is a bug, we will fix it in the next release. The divide-by-two logic is not working properly for the "datasheet Kv" vco model which is used for the 7010/7011. There is a quick workaround you can do, change the library file to use the ideal tuning law model - with the correct parameters this will result in identical operation: 1. find: c:\Program Files\Applied Radio Labs\ADIsimPL Ver2\Lib\VCO\AD_Integrated.lib 2. make a backup copy of the file 3. open the file with notepad 4. find the entry for the ADF7010 VCO, it should look like .model "ADF7010" fscale = 1M Kv = 80 V1 = .25 V2 = 2.75 F1 = 800 F2 = 1000 Ct = 5p PNTable = { 100000, -88, 1000000, -108 } .endmodel 5. delete the V1, V2, F1, F2 entries and replace them with F0 = 780, the result should look like: .model "ADF7010" fscale = 1M Kv = 80 F0 = 780 Ct = 5p PNTable = { 100000, -88, 1000000, -108 } .endmodel 6. save the file The program should now run correctly Peter White Applied Radio Labs

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