I am trying to simulate a PLL which uses very large N-Divider values, with typically the prescaler value set to it's max value=64. However ADISimPLL seems to default the P value to 16 and then outputs an error saying the VCO is out of range. I can manually then change the P value to 64 to fix the error when I'm using the ADF4113 but I can't seem to change it when using the ADF4118. Any ideas?
My setup: Freq. = 2GHz to 2.2GHz
Channel Spacing = 5kHz
Kv = 50MHz/v
Chip ADF4113/ADF4118
Passive 2-pole filter

This is a problem that we will fix - the software should select a suitable prescaler value in this situation. You are working around the problem correctly.

The reason you can't change the prescaler on the ADF4118 is that this chip only has a 32/33 prescaler. In fact the ADF4118 should not be appearing as an option for this design - it cannot achieve the division ratio required.