SimPLL

SimPLL is the easy way to design, optimise and simulate PLL frequency synthesizers. SimPLL accurately predicts the phase noise, reference spurs, lock time, modulation response and more.
Use SimPLL and get tough PLL designs right first time.
Download the FREE demo with interactive PLL tutorial here

Our Design File with technical notes on RF and PLL design

Free Design Tools from Analog Devices

ADIsimPLL is a custom version of SimPLL, preprogrammed with characteristics of Analog Devices PLL devices. the easy way to design, optimise and simulate PLL frequency synthesizers.

ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Users can optimise and simulate ultra low jitter clock products, and predict jitter performance.

ADIsimSRD Design Studio is a very powerful tool allowing real-time simulation and optimization of many of the parameters in a typical wireless system using the ADF7xxx family of transceivers and transmitters.